Expertise in SoC subsystem/IP design
Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog
In depth knowledge on RTL quality checks (Lint, CDC)
Knowledge of synthesis and low power is a plus
Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)
Good understanding of timing concepts
Knowledge of one or more of the interface protocols
a. PCIe
b. DDR
c. Ethernet
d. I2C, UART, SPI